Electron barrier height controlled interfaces of resistive switching layers in resistive random access memory cells

US9246087B1 · kind B1 · utility

Assignee

• INTERMOLECULAR, INC. · US

Inventors

• Yun Wang · San Jose, US
• Federico Nardi · San Jose, US

Key dates

• Filing date: Nov 24, 2014
• Grant date: Jan 26, 2016
• Expiry date: Nov 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B63/84

Abstract

Provided are resistive switching memory cells and method of forming such cells. A memory cell includes a resistive switching layer disposed between two buffer layers. The electron barrier height of the material used for each buffer layer is less than the electron barrier height of the material used for the resistive switching layer. Furthermore, the thickness of each buffer layer may be less than the thickness of the resistive switching layer. The buffer layers reduce diffusion between the resistive switching layer and electrodes. Furthermore, the buffer layers improve data retention and prevent unintentional resistive switching when a reading signal is applied to the memory cell. The reading signal uses a low voltage and most of the electron tunneling is blocked by the buffer layers during this operation. On the other hand, the buffer layers allow electrode tunneling at higher voltages used for forming and switching signals.