Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop
US9246347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jan 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J7/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.