Wafer-level testing method for singulated 3D-stacked chip cubes
US9250288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Oct 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.