Patterning assist feature to mitigate reactive ion etch microloading effect
US9252022B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes forming a masking layer on an upper surface of a semiconductor substrate. The masking layer is patterned to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element. An etching process is performed to form a plurality of semiconductor fins on the semiconductor substrate. The plurality of semiconductor fins include at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the patterning assist feature that reduces a loading effect that occurs during the etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.