System-in-packages and methods for forming same
US9252030B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.