Semiconductor device grid array package
US9252114B2 · kind B2 · utility
0Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Nov 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.