Non-volatile memory with silicided bit line contacts
US9252154B2 · kind B2 · utility
3Cited by
15References
20Claims
0Family size
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Key dates
| Filing date | Sep 30, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.