Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device

US9252215B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brian J. Greene · Wappingers Falls, US
• Arvind Kumar · Beaverton, US
• Dan M. Mocuta · Herent, BE

Key dates

• Filing date: Aug 17, 2015
• Grant date: Feb 2, 2016
• Expiry date: Aug 17, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.