Semiconductor component and method
US9257513B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Aug 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.