Method for producing a metal-gate MOS transistor, in particular a PMOS transistor, and corresponding integrated circuit
US9257518B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.