Nanowire transistor structures with merged source/drain regions using auxiliary pillars
US9257527B2 · kind B2 · utility
27Cited by
11References
10Claims
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Key dates
| Filing date | Feb 14, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.