Via structure, memory array structure, three-dimensional resistance memory and method of forming the same
US9257641B2 · kind B2 · utility
4Cited by
7References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Sep 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.