Bypass system and method that mimics clock to data memory read timing
US9263100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Feb 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.