Method and device for evaluating a chip manufacturing process
US9263154B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.