Integrated finFET-BJT replacement metal gate
US9263583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Oct 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0112
Abstract
A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.