Fin device with blocking layer in channel region
US9263587B1 · kind B1 · utility
14Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.