Packaging substrate and fabrication method thereof
US9265154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.