Enforcing a power consumption duty cycle in a processor

US9268393B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ankush Varma · Portland, US
• Krishnakanth V. Sistla · Beaverton, US
• Martin T. Rowland · Beaverton, US
• Brian J. Griffith · Auburn, US
• Viktor D. Vogman · Olympia, US
• Joseph R. Doucette · Waltham, US
• Eric J. Dehaemer · Shrewsbury, US
• Vivek Garg · San Mateo, US
• Chris Poirier · Fort Collins, US
• Jeremy J. Shrall · Portland, US
• Avinash N. Ananthakrishnan · Portland, US
• Stephen H. Gunther · Beaverton, US

Key dates

• Filing date: Nov 30, 2012
• Grant date: Feb 23, 2016
• Expiry date: Aug 2, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.