Flush operations in a processor
US9268575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are provided for flush operations in a processor. The apparatus comprises an out-of-order execution unit for processing instructions issued in-order from an instruction decoder for first and second threads and being configured to identify an errored instruction in a first thread. A retire unit includes a retire queue for receiving completed instructions from the out-of-order execution unit, the retire unit being configured retire older in-order first thread instructions until the errored instruction would be the next instruction to be retired, and then flushing the errored instruction and all later in-order first thread instructions from the retire queue. The method comprises determining that an errored instruction is being processed by an out-of-order execution unit of a processor and continuing to process to completion instructions earlier in-order from the errored instruction until the completion of the errored instruction. Following completion of the errored instruction, it is flushed along with all instructions later in-order than the errored instruction to recover the processor to a pre-error state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.