Error correction using multiple data sources
US9268635B2 · kind B2 · utility
13Cited by
7References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory and a controller. A method includes accessing data stored at the memory to generate a first logical page. The method further includes generating a second logical page. Generating the second logical page includes accessing parity information from the memory. The parity information is associated with the first logical page. The method further includes generating a third logical page. Generating the third logical page includes modifying a first value of the first logical page based on a second bit value of the second logical page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.