Techniques for determining victim row addresses in a volatile memory
US9269436B2 · kind B2 · utility
5Cited by
0References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.