Using stress reduction barrier sub-layers in a semiconductor die
US9269662B2 · kind B2 · utility
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1References
20Claims
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Key dates
| Filing date | Oct 17, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Nov 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.