Wafer level packaging techniques
US9269679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.