Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
US9269700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.