Insulation wall between transistors on SOI
US9269768B2 · kind B2 · utility
0Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2015 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.