Molded electronic package geometry to control warpage and die stress
US9269872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for a molded electronic package geometry that enables control of warpage and die stress. A mold tool can be closed to define a space or cavity about a semiconductor die disposed on a substrate. Once the mold tool is closed, a mold material can be applied to the space to produce a mold cap. The mold cap geometry can have a first surface that is in contact with the surface of the substrate and a second surface that is opposite the first surface. The second surface can define a tapered portion of the mold cap in which the larger thickness of the tapered portion of the mold cap is in proximity to the semiconductor die and the smaller thickness of the tapered portion of the mold cap is away from the semiconductor die. The thickness of the tapered portion can vary linearly or non-linearly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.