Ultrathin flip-chip packaging techniques and configurations
US9269887B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2015 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Feb 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include but are not limited to apparatuses and systems including microelectronic devices including a package substrate, a plurality of electronic components disposed on and electrically coupled with the package substrate at one or more sides of the package substrate, one or more hollow cavity sheet molds surrounding the plurality of electronic components and coupled with one or more sides of the package substrate, and a plurality of through-mold vias to couple the package substrate with an external surface of at least one of the one or more hollow cavity sheet molds. The microelectronic device may be a chip-scale package or module. Methods and systems for making the same also are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.