Handling virtual memory address synonyms in a multi-level cache hierarchy structure

US9274959B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Christian Habermann · Stuttgart, DE
• Christian Jacobi · West Park, US
• Gerrit Koch · Herrenberg, DE
• Martin Recktenwald · Eppelheim, DE
• Hans-Werner Tast · Holzgerlingen, DE

Key dates

• Filing date: Jul 18, 2014
• Grant date: Mar 1, 2016
• Expiry date: Jul 18, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1024
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Handling virtual memory address synonyms in a multi-level cache hierarchy structure. The multi-level cache hierarchy structure having a first level, L1 cache, the L1 cache being operatively connected to a second level, L2 cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory including directory entries having information of data currently stored in the L1 cache, the L2 cache being operatively connected to a third level, L3 cache. The first level cache is virtually indexed while the second and third levels are physically indexed. Counter bits are allocated in a directory entry of the L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first L1 cache line. A first search is performed in the L1 cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line.