Semiconductor package having a recess filled with a molding compound
US9275924B2 · kind B2 · utility
59Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Aug 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.