Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same

US9275934B2 · kind B2 · utility

Assignee

• Georgia Tech Research Corporation · US

Inventors

• Venkatesh Sundaram · Norcross, US
• Fuhan Liu · Atlanta, US
• Rao R. Tummala · Wappingers Falls, US
• Vijay Sukumaran · Atlanta, US
• Vivek Swaminathan Sridharan · Dallas, US
• Qiao Chen · Flower Mound, US

Key dates

• Filing date: Mar 3, 2011
• Grant date: Mar 1, 2016
• Expiry date: Mar 3, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.