Non-volatile memory array with concurrently formed low and high voltage logic devices

US9276005B1 · kind B1 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Feng Zhou · Ann Arbor, US
• Xian Liu · Sunnyvale, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Dec 4, 2014
• Grant date: Mar 1, 2016
• Expiry date: Dec 4, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.