Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same
US9276006B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2015 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jan 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
Abstract
A non-volatile memory cell including a substrate having first and second regions with a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over and insulated from a second portion of the channel region which is adjacent to the second region. The select gate includes a block of polysilicon material and a work function metal material layer extending along bottom and side surfaces of the polysilicon material block. The select gate is insulated from the second portion of the channel region by a silicon dioxide layer and a high K insulating material layer. A control gate is disposed over and insulated from the floating gate, and an erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.