Jeng-Wei Yang
28Patents
8h-index
17Co-inventors
68Inventor score
Filing activity: Sep 29, 2005 → Feb 18, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9887206B2 | Method of making split gate non-volatile memory cell with 3D FinFET structure | Electricity | 53 | Active |
| US9276006B1 | Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same | Electricity | 34 | Active |
| US9634019B1 | Non-volatile split gate memory cells with integrated high K metal gate, and method of making same | Electricity | 11 | Active |
| US9634018B2 | Split gate non-volatile memory cell with 3D finFET structure, and method of making same | Electricity | 11 | Active |
| US9379121B1 | Split gate non-volatile flash memory cell having metal gates and method of making same | Electricity | 10 | Active |
| US9496369B2 | Method of forming split-gate memory cell array along with low and high voltage logic devices | Electricity | 9 | Active |
| US9972630B2 | Split gate non-volatile flash memory cell having metal gates and method of making same | Electricity | 8 | Active |
| US9985042B2 | Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells | Electricity | 8 | Active |
| US9431407B2 | Method of making embedded memory device with silicon-on-insulator substrate | Electricity | 7 | Active |
| US10418451B1 | Split-gate flash memory cell with varying insulation gate oxides, and method of forming same | Electricity | 7 | Active |
| US9721958B2 | Method of forming self-aligned split-gate memory cell array with metal gates and logic devices | Electricity | 5 | Active |
| US9793281B2 | Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same | Electricity | 5 | Active |
| US9484261B2 | Formation of self-aligned source for split-gate non-volatile memory cell | Electricity | 4 | Active |
| US10714634B2 | Non-volatile split gate memory cells with integrated high K metal control gates and method of making same | Electricity | 4 | Active |
| US10608090B2 | Method of manufacturing a split-gate flash memory cell with erase gate | Electricity | 4 | Active |
| US10249631B2 | Split gate non-volatile flash memory cell having metal gates | Electricity | 3 | Active |
| US10312246B2 | Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling | Electricity | 2 | Active |
| US9793280B2 | Integration of split gate flash memory array and logic devices | Physics | 2 | Active |
| US9972493B2 | Method of forming low height split gate memory cells | Electricity | 2 | Active |
| US7358559B2 | Bi-directional read/program non-volatile floating gate memory array, and method of formation | Electricity | 2 | Expired |
| US9293358B2 | Double patterning method of forming semiconductor active areas and isolation regions | Electricity | 2 | Active |
| US9793279B2 | Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing | Electricity | 1 | Active |
| US10607703B2 | Split-gate flash memory array with byte erase operation | Electricity | 1 | Active |
| US10141321B2 | Method of forming flash memory with separate wordline and erase gates | Physics | 1 | Active |
| US9659946B2 | Self-aligned source for split-gate non-volatile memory cell | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.