Dual silicide formation method to embed split gate flash memory in high-k metal gate (HKMG) technology
US9276010B2 · kind B2 · utility
9Cited by
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20Claims
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Key dates
| Filing date | Jun 5, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jun 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.