Semiconductor device and method of calibrating warpage testing system to accurately measure semiconductor package warpage
US9279673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.