Refresh hidden eDRAM memory
US9281045B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.