Read clock forwarding for multiple source-synchronous memory interfaces
US9281049B1 · kind B1 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.