One time programmable memory cell capable of reducing leakage current and preventing slow bit response
US9281074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.