Patent · US Active

Method comprising applying an external mechanical stress to a semiconductor structure and semiconductor processing tool

US9281252B1 · kind B1 · utility

5Cited by

0References

24Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Alexander Würfel · Dresden, DE
Moritz Andreas Meyer · Pulheim, DE

Key dates

Filing date	Oct 24, 2014
Grant date	Mar 8, 2016
Priority date	—
Expiry date	Oct 24, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/12
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes providing a semiconductor structure. An external mechanical stress is applied to the semiconductor structure. One or more semiconductor manufacturing processes are performed while the external mechanical stress is applied to the semiconductor structure. The one or more semiconductor manufacturing processes provide one or more material layers having an intrinsic stress at the semiconductor structure. After performing the one or more semiconductor manufacturing processes, the external mechanical stress is removed from the semiconductor structure. The removal of the external mechanical stress at least partially relaxes the intrinsic stress of the one or more material layers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.