Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9281296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.