Patent · US Active

Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit

US9281807B1 · kind B1 · utility

10Cited by

4References

17Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Pierre Maillard · San Jose, US
Praful Jain · San Jose, US
Michael J. Hart · Palo Alto, US
Sundeep Ram Gopal Agarwal · Hyderabad, IN
Austin H. Lesea · Los Gatos, US
Jun Liu · 红钢城街道, CN

Key dates

Filing date	Jun 9, 2014
Grant date	Mar 8, 2016
Priority date	—
Expiry date	Jun 9, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/356156
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.