Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch
US9287183B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/24
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.