Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations
US9287185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and systems determine an original statistical variance of an original failure distribution of a component (that is common to all chips tested) that occurs during manufacturing of wafers containing such chips. These methods and systems determine a first statistical variance of a reconstructed failure distribution, relative to sample size; and determine a second statistical variance of a mean time to failure of the component, relative to sample size. The first and second statistical variances are combined into a total reconstruction variance. Methods and systems determine whether the original statistical variance is less than the total reconstruction variance to identify whether the process of creating the reconstructed failure distribution can be used. Therefore, these methods and systems prohibit testing of the additional wafers manufactured using the specific wafer design and manufacturing process when on the original statistical variance is less than the total reconstruction variance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.