Method and apparatus for floating or applying voltage to a well of an integrated circuit
US9287253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.