Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

US9287271B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Kuo-Chen Wang · Boise, US
• Sriraj Manavalan · Boise, US
• Wei-Ming Liao · Taoyuan, TW

Key dates

• Filing date: Apr 29, 2015
• Grant date: Mar 15, 2016
• Expiry date: Apr 29, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/63

Abstract

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.