Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same

US9287357B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Mark S. Rodder · Dallas, US
• Borna J. Obradovic · Leander, US
• Rwik Sengupta · Austin, US
• Dharmendar Reddy Palle · Austin, US
• Robert C. Bowen · Lucas, US

Key dates

• Filing date: Jun 11, 2015
• Grant date: Mar 15, 2016
• Expiry date: Jun 11, 2035

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/755
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.