Detection of memory address aliasing and violations of data dependency relationships
US9292294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Nov 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.