Integrated circuit with increased fault coverage
US9297855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic design automation (EDA) tool for increasing the fault coverage of an integrated circuit (IC) design includes a processor that inserts at least one XOR gate, an AND gate, an OR gate and a multiplexer between observation test points and an existing first scan flip-flop of the IC design. The XOR gate provides an observation test signal to the first scan flip-flop by way of the AND gate, the OR gate, and the multiplexer such that the observation test signal covers the presence of faults at the observation test points. The first scan flip-flop outputs a data input signal, a set of test patterns, and a first set of test signals based on the observation test signal to indicate whether the IC design is faulty or not. A testable IC that can be structurally tested is fabricated using the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.