Patent · US Active

Implementing MISR compression methods for test time reduction

US9297856B2 · kind B2 · utility

2Cited by

6References

9Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Steven M. Douskey · Rochester, US
Mary P. Kusko · Poughkeepsie, US
Cedric Lichtenau · Stuttgart, DE

Key dates

Filing date	Oct 23, 2013
Grant date	Mar 29, 2016
Priority date	—
Expiry date	Feb 1, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/31703
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.