Patent · US Active

Built-in self test (BIST) with clock control

US9298572B2 · kind B2 · utility

4Cited by

13References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Nisar Ahmed · Richardson, US
Anurag Jindal · Singapore, SG
Nipun Mahajan · Lawrenceville, US

Key dates

Filing date	Aug 14, 2013
Grant date	Mar 29, 2016
Priority date	—
Expiry date	Oct 27, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318552
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.